Nader Jedidi

Postdoctoral Fellow with Pr. Dominique Drouin, Department of Electrical Engineering. My postdoctoral research focuses on a number of axes in relation with the fabrication of Single Electron Transistors:
i. Designing and characterizing electrical test structures, for Titanium chemical mechanical polishing monitoring,
ii. Establishing an accurate resistivity versus titanium thickness diagram, at sub 100nm thicknesses.

I was in charge of developing and optimizing the process of a new power semiconductor device, namely the Trench MOS Barrier Schottky Rectifier (TMBS).

The objective of my research is to design and develop solutions to address the large variations of critical device parametric characteristics of a CMOS logic 0.13µm technology. My activities can be summarized in four main points:

- Preventive Maintenance (PM) and aging effect of Plasma Etching Equipment: Participated actively in building predictive models of gate critical dimension (CD) based on equipment parameters and photoresist CD,

- Analysis of semiconductor production test data and root cause identification: Carried out a measurement campaign (parametric test characteristics, gate CD, gate oxide thickness, etc) and demonstrated
through a statistical analysis that the biggest cause of parametric transistor variability and hence Yield loss is large gate line-width (CD) variation. The post-exposure bake (PEB) plate temperature uniformity, at the gate photolithography step, has been identified as one of the root causes of the latter within wafer component,

- The run-to-run controller project: Developed a feed-forward run-to-run controller from gate etching to pocket implantation allowing a 40% reduction of the lot-to-lot main parametric characteristics variations, and saving approximately 10000€ per week along 2007,

- Designed and simulated an in-line estimator of the 193nm lithography process, capable of identifying the contributions of the variation sources (process and metrology tools, reticles, etc) to the critical dimension (CD) deviation.

Certificate of Excellence for project achievement.

Internship within the Research and Development team, I was in charge of

- Developing a number of recipes relative to atmospheric pressure oxidation and annealing,

- Optimizing the deposition of low stress silicon nitride films by low-pressure chemical vapor deposition LPCVD (horizontal 6" furnace): literature review and design of experiments.

Defined the appropriate technical solution to treat greenhouse emissions (PFC) of dry etch equipment.