Paris
RETROUVEZ GRATUITEMENTLe résultat des européennes à Paris.
Summary:
- Management on several sites (France, China)
- Method & tools
- Electronic & 3D simulation tools
Simulation team manager
VALEO (Automotive Industry) / Group Electronic Expertises and development services (GEEDS)
January 2009 - present
Manage a simulation team (14) with the following skills:
- Finite element simulation around Thermal / Mechanical / vibration
- Mechatronic system
- Electronic system
Define and deploy the standards and the methodologies on the tools (FEA, Mechatronic, Electronic) in the Valeo group
Provide and promote a service mode in the Valeo group
Automotive ASIC expertise engineer / simulation expertise engineer
VALEO (Automotive Industry)
June 2005 – December 2008
leader of a VALEO program working group: System
simulation
- Project leader of a collaborative project with academics: HECOSIM
- Evaluated and offered technical support on new automotive ASIC
development
- Modelized and build new automotive architecture within VHDL-AMS
language
- Implemented digital block on FPGA
RF & Mixed Signal Group Leader
Wavecom (Semiconductors Industry)
August 2001 – March 2005 (3 years 8 months)
- Group Leader: Defined design tasks and tracked design progress
of 8 design engineers with a budget of €2M
- Technical leader: Defined analog specifications with or without
architects, technical interface for project leaders
- Top-down design methodology (Spectre-Verilog) on complex
Analog & Mixed Signal IC: ADC, DAC
- EDA tools: Evaluated, purchased, installed and offered
technical support on Cadence, Mentor Graphics, Xpedion
Senior Analog Design Engineer
PHILIPS (Semiconductors Industry)
February 2001 – July 2001 (6 months)
Design & Layout on CMOS 0.18µm technology:
- Participated in IQDAC UMTS: Hybrid I R/2R DAC 10bits@30.72MHz
- Created I R/2R DAC C Model in order to evaluate the max
mismatch on fets and poly resistors acceptable
- Realized 32.768 kHz crystal oscillator
Analog Design Engineer
ATMEL (Semiconductors Industry)
August 1996 – January 2001 (4 years 6 months)
- Responsible for Oscillator & PLL library and 2 analog
designers:
* Supported external and internal customers for use of
Oscillator & PLL libraries
* Defined and maintained Oscillator & PLL library on the latest
technologies
* Tracked and improved cell yields of libraries on the customer
projects
- Responsible for technical interface on the Data Codec project
(sigma delta)
* Participated in analog specifications with the IP provider
and the customer, tracked external design progress
* Defined and implemented test chips
* Simulated test chips in mixed signal mode
* Provided support for designers, product and test engineers:
Training, technical support
- Design & Layout on CMOS technology:
* Implemented and validated 1-20MHz & 32.768kHz crystal
oscillator, SAR ADC 8 bits @ 400 kHz, supply monitor,
bandgap, LDO regulator, RC oscillator, opamp class A
Engineering School ENSI-Caen
Master, Microelectronics, September 1995
Mes compétences :
Management
Electronic simulation
Project management
